Konami 051962 schematic (Patreon)

The Konami 051962 chip tracing was finished a few days ago. That's about one fifth of the video logic used by the previously mentionned games. 

This one is used in pair with the 052109, which I'll work on next.
It serves 4 main purposes:

* It lets the main 8-bit CPU read the 32-bit wide GFX ROM bus to compute the startup test checksums. A small surprise here: the CPU can also write to the BUS ! Did Konami plan using using GFX RAM ? Or is this a devkit remnant ?

* It generates the video sync signals.

* It re-times the consecutive GFX ROM accesses for the A, B and FIX layers to present the pixel data all at once for the 053251 mixer chip (which I already traced in 2019), effectively doing a serial to parallel conversion.

* It uses the fine scrolling values and the horizontal-flip flag to extract the required pixel from the 8-pixel rows output by the GFX ROMs.

Overall it's a simple chip, using design choices which seem inherited from the 007121.
For example, updating of the delaying registers isn't done use clock gating. Instead, they're all clocked with the main system clock, and either fed back their own output (hold) or fed the previous stage's output (update).
I'm not sure why clock gating wasn't used, since this solution takes more space.
Design re-use, or minimal clock skew constraint ?

The schematics and the svg die overlay can be found here: https://github.com/furrtek/VGChips/tree/master/Konami/051962

As written above, the next chip I'll dig into is the 052109. This one generates the addresses for the GFX ROMs from the tile codes and attributes stored in VRAM. It also generates IRQs.