Progress June I - Component placement (Patreon)

Quick update with a pretty bad looking 3D preview of the testing board.

Routing is done locally but the groups aren't connected together yet, so stuff can (and will) still be moved around.

To reduce the number of I/Os needed on the FPGA board (which will be stuck vertically), I'm using an additional CPLD to do address decoding. That way it can just sit on the already available 68k address bus, and output enable/clock signals to a bunch of HC245's which will gate data to and from the data bus.
This brings the count of PLDs to 3: The main FPGA, the pixel serializer CPLD needed for MVS carts, and the address decoding CPLD.

As you can see, there will be a JAMMA edge along with a DIN RGB output, joypad connectors obviously, a memory card slot and outputs for credits and marquee displays.

The required ROMs are pretty large but I can't do much about it since SMT flash sockets are expensive and the required data doesn't fit in the FPGA itself. Also having an original AES system ROM plugged in can look cool :)

Feel free to comment about the placement and availability of I/Os here or on Twitter !