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Short video update as I didn't have much time to spend on the project these last months. I did get a minimal setup to run on the Terasic DE-1 dev board (Altera FPGA).

It runs the TG68k 68000 core, the reverse-engineered LSPC2-A2 and NEO-B1 video chips, along with various SNK chips for glue logic, decoding, I/O...

The small program sets up fix tiles and sprites in VRAM and allows to move a block with the joypad. The shrinking parameters can also be modified to check that the logic works correctly.

The Verilog code was directly taken from the simulation project, with slight modifications to allow the use of block RAM instead of ROMs, and the addition of an initialization state machine to load the "cartridge" with pre-defined data from flash.

I only met minor issues related to the use of delay cells in LSPC2 and NEO-B1, which I simulated with #delays in the simulation code but which can't be synthesized for "real" on the FPGA. Luckily, replacing them by registers clocked by chosen edges of the main 24MHz clock solved the issues.

No further progress on the test board and the YM2610 soundchip for now.

Files

NeoGeo FPGA project: minimal cart and video testing on Terasic DE-1

Not exactly 330 MEGS but size isn't important, right ?

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