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Here it is ! After I finished tracing the NEO-B1 die picture earlier than I thought (lots of parallel stuff in it), I translated the schematic to verilog and spent about 5 days trying to get the simulation to start up Metal Slug and display the iconic eye-catcher animation.

Two bugs were caused by missing characters: One "&" causing glitches on horizontally scaled sprites, and one ~ preventing sprite chaining from working.
Another bug was caused by the 68k core I'm using (TG68K) not liking Z's on its data input bus when reading bytes. I was surprised that all the BIOS self-tests passed with byte wide read-modify-write instructions not working at all !

So finally, here are the 295 frames output from a simulation that lasted 3 hours and 22 minutes. Yeah, 5 seconds of video.

A slight problem related to video sync remains. As it can be seen on the video, the palette updates are being done outside of v-blank. It seems that the v-blank interrupt is triggered 16 lines too late.
Not really a big deal, probably used a wrong bit on the line counter :)

Next steps are further testing in simulation, continuing work on the YM2610 and the verification board layout, which I'll try to order during June.

As I will be buying more components for the verification board to check their footprints, and as this is quite the milestone, this is a paid post.
Thanks A LOT to all the supporters for helping me keep this project going :)

Files

NeoGeo FPGA project 28 April 2018

Simulation time: 3 hours 22 minutes. Running mslug romset, eye-catcher displays for the first time :)

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