Progress April I - Heartbeat (Patreon)

I'm still alive and the tracing of NEO-B1 is going smoothly.
I should be able to start translating the schematic to Verilog next month.

No surprises in this chip, everything is pretty straightforward except for a few odd uses of shift registers I wouldn't have guessed. Also lots of logic is used up by a test mode giving direct access to the SRAM cells. This was certainly used before assembly to see if no bits were faulty.

Lots of silicon for something that was only used once at the factory and never again !