Progress February I - Tracing done ! (Patreon)

It took about 110 hours to completely trace the LSPC2 chip die and draw the schematic using symbols representing the cells.

As already said, my wrist was giving up sometimes but it always recovered after some sleep, so no serious damage there :)
Apart from a few tedious fixes, it really wasn't that much of a pain thanks to the very clear pictures John took.

You can navigate the rendered picture here:

http://furrtek.free.fr/lspc2/

(Not on Github since they don't like large files and it has limited usefulness anyways).

More useful info can be found at another spot on my website:

http://furrtek.free.fr/?a=fujiga

Notes about the process of identifying Fujitsu gate array cells and laying down a schematic from them. This might help others who would like to dig into similar chips. I've seen the typical Fujitsu markings on Irem/Nanao and Capcom chips at least.

I just began translating the schematic to Verilog. The updated source on Github now generates a video sync signal perfectly identical to the AES home console. It isn't much, but it proves that the whole process is worth it :)