Konami 053260 tracing done (Patreon)

First time tracing a Toshiba gate array and it was awful. Not 007121-awful, but still.

Identifying the cells and reverse-engineering them required individual stitches at 50x magnification but apart from that, it was rather easy.

The routing however took much more time to trace than expected. Like Oki, Toshiba didn't have very big cells such as counters and 4-bit adders, everything is decomposed as registers, combinational gates and muxes. This allows for more flexibility (the array won't get jammed with very tall gates) but makes reverse-engineering much more time consuming.

Fujitsu for example had a 4-bit counter cell. These were always the same and the i/o connection points were always in the same place. Once the cell is identified, it can be seen like a tiny self-contained logic chip with a known "pinout".
Toshiba and Oki counters however are made of about 10 simpler cells which are spread apart and arranged like the place & route tool decided to at the time the chip was designed. Same function, a lot more work.

Now it's time to actually draw the schematic !

Since work on this chip until now has mostly consisted of drawing lines, I wondered what would be the total length of all traces if they were straightened out and put end to end. I wrote a small python script to list all the paths on a given layer, interpret the drawing commands to extract the line lengths, add everything up and scale the final result according to the dimensions of the full die as a reference.

The result is 8.17 meters (26.8ft) of traces on a 49mm² piece of silicon.
I can't even imagine how much higher that ratio would be with any of today's mobile processors...